1. Field of the Invention
The present invention relates to digital memories and, more particularly, to techniques for repairing digital memories having multiple redundant elements.
2. Related Art
Integrated circuits are becoming increasingly small and densely packed. It is now possible, for example, to manufacture individual digital memory cells having an area of less than one square micron, and to pack hundreds of millions of transistors on a memory chip that is smaller than a dime. Due to uncontrollable variations in the manufacturing process, it is not possible to manufacture such memory chips perfectly. Any particular memory chip may include any number and variety of defects. For example, one or more memory cells on a chip may be defective and therefore be unable to store data reliably.
For a memory chip to be usable, however, the chip must be functionally indistinguishable from a chip having no defects. Because it is not possible to manufacture an actual defect-free chip, various techniques have been developed for automatically repairing defective chips so that they can provide the same functionality as a defect-free chip. Although it may not be possible to repair all defects in all chips, the ability to make even some chips usable by repairing them may increase the production yield of a particular batch of chips, thereby increasing the efficiency of the manufacturing process.
One technique that has been employed to repair chips is to provide redundant circuit elements on the chips that may be substituted for key circuit elements that prove to be defective. During testing of a chip, the defective portion of the circuit may be identified and the redundant circuit element, if one exists, may be activated by opening an associated fuse or similar mechanism. The redundant circuit element thereafter substitutes for and effectively replaces the original defective circuit element, thereby repairing the chip and making it usable. Redundancy is especially suited for repetitive circuits having a large number of repeating elements arranged in some form of array, such that a redundant circuit element can replace a single defective circuit element in a collection of circuit elements.
Memory chips are one example of such repetitive circuits. The memory in a memory chip is arranged in rows and columns. The redundant circuit element in such a chip may, for example, be a single memory cell, a row or collection of rows of memory cells, or a column or collection of columns of memory cells. If, for example, one cell in a given column is defective, the cell may be classified as defective. The defective cell, the column (or row) containing it, or the collection of columns (or rows) containing the defective cell may effectively be replaced by a redundant cell, row, column, or collection of rows or columns. In this way the chip may be made fully operational. Such repair makes it possible to use the memory chip reliably, thereby increasing the production yield by avoiding the need to discard the memory chip.
A memory “IO” is a combination input/output interface for transmitting data to and from a memory chip. A single IO may be connected to a particular array or sub-array of memory on the chip. For example, each IO on a chip may be connected to memory arrays each having 8 columns and 256 rows. If an individual cell, column, or row in an array coupled to a particular IO is defective, it may be possible to repair the individual cell, column, or row using conventional repair techniques. If conventional repair techniques fail, however, techniques also exist for repairing the IO itself by effectively replacing it with a redundant IO coupled to an entire redundant memory array.
Furthermore, the co-pending and commonly-owned patent application Ser. No. 09/919,091, entitled “A Data-Shifting Scheme for Utilizing Multiple Redundant Elements,” filed on Jul. 31, 2001, Attorney Docket No. 10004359-1, discloses techniques for shifting cache input and output data so that such data are routed around as many as two defective cache IOs. The circuit elements (e.g., multiplexors) which perform such data shifting must be configured to route data around the particular cache IOs (if any) which are determined to be defective. It is desirable for such configuration to be performed automatically in response to identification of the particular cache IOs (if any) which are determined to be defective. Performing such configuration automatically and accurately for a wide variety of defects presents particular challenges given the variety of permutations in which zero, one, or two cache IOs may be defective and given the fact that it may not be possible to detect defective cache IOs with perfect accuracy.
What is needed, therefore, are techniques for configuring a cache to repair multiple defective IOs.